The present invention relates, in general, to ultra-large scale integration of electronic devices, and more particularly to single crystal beam microstructures formed on a substrate and which incorporate transistor devices. Plural beams may be provided which are electrically isolated from each other both horizontally and in vertical stacks, and isolated from the adjacent substrate so as to permit minimum spacing between adjacent transistor devices. The beams may be movable or stationary and thus the invention further relates to transistor devices mounted in microstructure beams incorporating movable tips for the amplification of currents in such tips.
The trend towards ultra-large scale integration (ULSI) of electronic devices requires ultra-small transistors and isolation structures. However, present device isolation technology places a serious limit on the minimum spacing between electronic devices such as transistors, for either p-n junction space charge region isolation or dielectric isolation increases the area of the substrate which must be devoted to an isolated transistor. This spacing requirement is further increased by the need to have large area planar contacts to the transistors. Many schemes have been suggested to increase the density of electronic devices; for example, it has been suggested that the transistor spacing in ULSI can be reduced by making MESA transistors with sidewall contacts or sidewall silicon gate structures. However, these MESA structures are still connected to the substrate, so electrical isolation is still necessary. The steps required for isolation of these non-planar structures reduces the ultimate circuit density and usually increases the complexity of the fabrication process. Thus, there is a need for an improved technique and structure for isolating transistors in integrated circuits.
For over thirty years, designers of integrated circuits have attempted to form silicon on insulator (SOI) device structures which would simplify transistor-to-transistor isolation spacing, would reduce parasitic capacitance and would thereby offer higher density integrated circuits with improved performance, as by providing faster transistors. The main disadvantages of SOI technology include inferior single crystal silicon material, very high substrate cost, and poor silicon-insulator interface characteristics, and accordingly such devices have not been completely satisfactory and have not provided the sought-after solution for isolating transistors.
Recent developments in microstructure technology for use with integrated circuits have led to the development of nanometer scale tips and opposed tips which are mounted on relatively movable microstructure beams, the tips being connected through the beams to integrated circuits in surrounding substrates. Such tips may be used to sense tunneling currents, for example, with the beams or with conductive layers on the beams transferring the sensed currents to external circuitry in the surrounding substrate. However, such currents are extremely small and the ability to transmit these currents to the surrounding substrate is a limiting factor in the utilization of microstructure tip technology.